1. Field of the Invention
This invention relates to a verification method of layout patterns of logical integrated circuits.
2. Description of the Related Art
Generally, parasitic capacitance is generated in layout design of logical integrated circuits. Parasitic capacitance increases gate delay and can be a cause of malfunctioning of finished products. Conventionally, in order to avoid malfunctioning, wiring on circuits that can significantly affect the delay time is marked beforehand, and is specially treated. In manual design the designers try to shorten the wiring as much as possible, and in automatic layout design parameters are specified so that the length of the wiring is limited.
In the conventional method described above, it is almost impossible to individually limit the length of wiring, considering the load capacitance caused by differences in output gates, and relative control of delay time has been a time consuming task. On the other hand, software calculating parasitic capacitance after layout design is available on the market. There is however, no foolproof way to utilize this software, and manual checking has been unavoidable.